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3) The verification process can be incremental and start as soon as the first application is available. (4) Functional verification is simplified, since bugs caused by, for instance, race conditions in the integrated application, are independent of other applications. Another benefit of composability is that independent applications create well-defined liabilities, which is important if applications are developed by different parties [97]. IP protection is furthermore improved, since the verification process no longer requires the IP components of independent software vendors to be shared.

An illustration of a basic memory controller is provided in Fig. 1. We use this architecture as a starting point and extend it with additional elements throughout this chapter until we reach the final design, previously shown in Fig. 12. 2 Predictable SDRAM Back-End As previously mentioned, our approach to predictable memory controllers requires a useful bound on: (1) the bandwidth offered by the memory, and (2) the time to serve a request. Satisfying these requirements is straight-forward for stateless Zerobus-turnaround (ZBT) SRAM memories, where the available bandwidth simply corresponds to the product between the width of the memory interface and the clock frequency, and a word is served with a fixed latency of one clock cycle.

The size of the atoms are fixed and determined at design time. The size of an atom is chosen to be the minimum request size that can be efficiently served by the resource. For an SRAM, the natural service unit is a single word, but it is much larger for an SDRAM with predictable memory patterns. In this case, the service unit might be between 16 and 256 words, depending on the memory device and the patterns. Using fixed-sized requests in the memory controller furthermore simplifies other blocks in the architecture, resulting in a faster implementation.

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